1. Field of the Invention
The present invention relates to optical and X-ray lithography technologies applied for manufacturing a semiconductor integrated circuit, a liquid crystal panel and the like, more particularly to a mask data generating apparatus, a computer implemented method for generating mask data and a computer program for controlling the mask data generating apparatus for performing correction processing of mask data.
2. Description of the Related Art
In a lithography technology used for manufacturing a semiconductor integrated circuit, the degree of integration of devices merged in a wafer has increased year by year, thus reducing a design rule thereof. Accordingly, optical proximity effect has been a significant problem. The optical proximity effect is a phenomenon that, when advanced miniaturization of a design pattern causes patterns to come in proximity to each other by approximately a wavelength of light or under a wavelength of light, the patterns are not transferred in accordance with designed shape and dimension on the wafer. “Optical proximity effect” was a term originally used regarding an effect caused by optical factors in pattern transfer; however, nowadays, it generally means an effect caused throughout an entire wafer processes.
In order to achieve a desired device performance, it is necessary to realize desired dimension and shape of the design pattern with predetermined precision on the wafer. Consequently, optical proximity effect correction (OPC) has been keenly studied in recent years, in which a pattern deviation occurs in process is previously compensated on a mask. OPC has been extensively studied as one type of resolution enhancement technologies (RET), and thus various techniques are now proposed and implemented.
In OPC, each edge of correction target pattern is divided in appropriate length, and a correction value is calculated regarding each divided edge. The correction value is acquired by iteranting a process simulation on arrangement in the vicinity of the edge to be corrected. In a layout of a critical design rule, spots that require correction to satisfy a desired precision have a tendency to increase. Thus, the number of times of performing the process simulation is increased, and as a result, a lot of time is needed for correction calculations. Accordingly, there is an urgent need to reduce calculating time. In consideration for the above situation, it is necessary to shorten correction time by efficiently grouping the point on which the process simulation for correction value calculation is performed and by calculating all at once in OPC.
According to the paper titled “First Proximity Collection With Zone Sampling”, described in Optical Laser Microlithography VII (Proc. SPIE Vol. 2197, p.p. 294 to 301) and the paper titled “Using Behavior Modeling For Proximity Collection”, described in the same (Proc. SPIE Vol. 2197, p.p. 371 to 376) published in May 1994, when optical proximity effect correction is performed for input data, each edge of a pattern to be corrected is divided into an appropriate size, and a correction value calculating point (a target point) is set for each divided edge. Moreover, the correction value at each correction value calculating point is acquired by performing process simulation with respect to a small area of about 2 to 4 μm in the vicinity of the point for each point. A correction target pattern is prepared by performing pattern data processing in which the correction value calculated at the correction value calculating point is applied to each divided edge and each edge thereof is moved.
The above-described technique will be described more concretely below. A pattern to be corrected is selected as shown in FIG. 1A, and each edge of this pattern to be corrected is divided based on a specified method as shown in FIG. 1B. Then, as shown in FIG. 1C, a point for calculating a correction value (hereinafter referred to as a “correction value calculating point”) is set for each divided edge. The correction value at each correction value calculating point is acquired by using the process simulation. In order to acquire a correction value of an edge 41 in FIG. 1C, for example, a point 42 is taken as the correction value calculating point, and the process simulation is performed with respect to a small area in the vicinity of the point 42 (a process simulation radius 43) as shown in FIG. 1D. The correction target pattern is prepared by performing pattern data processing in which the correction value is calculated by repeating the process simulation as needed, the correction value calculated at each correction value calculating point is applied to each edge and each edge is moved.
However, in a layout of a critical design rule, since the edge of the pattern is divided into minute pieces for high-precision correction thereof, the number of correction value calculating points is increased. In response to this increase, the number of times of executing the process simulation is also increased. As a result, a lot of time is required for correction calculation. Moreover, in order to calculate the correction values in one point, it is necessary to perform the simulation by overlapping arrangements in the vicinity of the points. Consequently, for example, in the case where the correction value calculating points are densely arranged such as in a memory cell, a memory cell peripheral portion and a cell wiring portion, the simulation is redundantly performed a plurality of times for the same region, leading to an increase in the simulation time. As a result, a data processing time is inevitably increased.
The inventors of this application found out the following. Specifically, that the simulation time can be shortened and the correction value calculating points can be calculated at a higher speed, by grouping the correction value calculating points into a fixed rectangular region and by performing the grouping into the rectangular region at a plurality of spots.